MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 474

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 16 Debug Module (DBGV1)
The DBG in DBG mode includes these distinctive features:
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Three comparators (A, B, and C)
— Dual mode, comparators A and B used to compare addresses
— Full mode, comparator A compares address and comparator B compares data
— Can be used as trigger and/or breakpoint
— Comparator C used in LOOP1 capture mode or as additional breakpoint
Four capture modes
— Normal mode, change-of-flow information is captured based on trigger specification
— Loop1 mode, comparator C is dynamically updated to prevent redundant change-of-flow
— Detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are
— Profile mode, last instruction address executed by CPU is returned when trace buffer address is
Two types of breakpoint or debug triggers
— Break just before a specific instruction will begin execution (tag)
— Break on the first instruction boundary after a match occurs (force)
BDM or SWI breakpoint
— Enter BDM on breakpoint (BDM)
— Execute SWI on breakpoint (SWI)
Nine trigger modes for comparators A and B
— A
— A or B
— A then B
— A and B, where B is data (full mode)
— A and not B, where B is data (full mode)
— Event only B, store data
— A then event only B, store data
— Inside range, A address B
— Outside range, address
Comparator C provides an additional tag or force breakpoint when capture mode is not configured
in LOOP1 mode.
Sixty-four word (16 bits wide) trace buffer for storing change-of-flow information, event only data
and other bus information.
— Source address of taken conditional branches (long, short, bit-conditional, and loop constructs)
— Destination address of indexed JMP, JSR, and CALL instruction.
— Destination address of RTI, RTS, and RTC instructions
— Vector address of interrupts, except for SWI and BDM vectors
storage.
stored in trace buffer
read
MC9S12E128 Data Sheet, Rev. 1.07
or address B
Freescale Semiconductor