MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 199

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out
period. A premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
4.5.3
The on-chip voltage regulator detects when V
power-on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered
the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates
a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows
the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock
mode.
Figure 4-26
and when the RESET pin is held low.
Freescale Semiconductor
Power-On Reset, Low Voltage Reset
and
Figure 4-27
Internal RESET
RESET
Internal POR
Internal RESET
RESET
Internal POR
Figure 4-26. RESET Pin Tied to V
show the power-up sequence for cases when the RESET pin is tied to V
Figure 4-27. RESET Pin Held Low Externally
MC9S12E128 Data Sheet, Rev. 1.07
DD
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self-Clock Mode)
128 SYSCLK
) (
to the MCU has reached a certain level and asserts
) (
128 SYSCLK
) (
) (
) (
) (
64 SYSCLK
DD
64 SYSCLK
(by a Pull-Up Resistor)
Chapter 4 Clocks and Reset Generator (CRGV4)
DD
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