MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 357
MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
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11.4
11.4.1
A block diagram of the PMF is shown in
generators (A, B, and C) or just a single generator (A). PWM0 and PWM1 constitute Pair A, PWM2 and
PWM3 constitute Pair B, and PWM4 and PWM5 constitute Pair C.
11.4.2
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the bus
clock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Each
prescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is set
and a new PWM reload cycle begins.
11.4.3
Each PWM generator contains a 15-bit up/down PWM counter producing output signals with
software-selectables:
11.4.3.1
Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs.
Freescale Semiconductor
•
•
•
Alignment—The logic state of each pair EDGE bit determines whether the PWM pair outputs are
edge-aligned or center-aligned
Period—The value written to each pair PWM counter modulo register is used to determine the
PWM pair period. The period can also be varied by using the prescaler
— With edge-aligned output, the modulus is the period of the PWM output in clock cycles
— With center-aligned output, the modulus is one-half of the PWM output period in clock cycles
Pulse width—The number written to the PWM value register determines the pulse width duty cycle
of the PWM output in clock cycles
— With center-aligned output, the pulse width is twice the value written to the PWM value register
— With edge-aligned output, the pulse width is the value written to the PWM value register
Functional Description
Block Diagram
Prescaler
PWM Generator
Alignment
ALIGNMENT REFERENCE
UP/DOWN COUNTER
DUTY CYCLE = 50%
PWM OUTPUT
MODULUS = 4
Figure 11-41. Center-Aligned PWM Output
MC9S12E128 Data Sheet, Rev. 1.07
Figure
11-1. The MTG bit allows the use of multiple PWM
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
357
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