MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 392

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
12.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: anytime
Write: anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 4 and 5 are concatenated, channel 4 registers become the
high-order bytes of the double-byte channel. When channels 2 and 3 are concatenated, channel 2 registers
become the high-order bytes of the double-byte channel. When channels 0 and 1 are concatenated,
channel 0 registers become the high-order bytes of the double-byte channel.
Reference
PWM function.
392
Reset
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
Field
5
4
3
2
1
0
W
R
Section 12.4.2.7, “PWM 16-Bit Functions,”
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
PWM Control Register (PWMCTL)
0
0
7
= Unimplemented or Reserved
CON45
0
6
Figure 12-8. PWM Control Register (PWMCTL)
Table 12-8. PWMCAE Field Descriptions
CON23
MC9S12E128 Data Sheet, Rev. 1.07
0
5
CON01
0
4
Description
for a more detailed description of the concatenation
PSWAI
0
3
PFRZ
0
2
Freescale Semiconductor
0
0
1
0
0
0