MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 178
MC9S12E128CPV
Manufacturer Part Number
MC9S12E128CPV
Description
Microcontrollers (MCU) 16 Bit 16MHz
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12E128CPV.pdf
(606 pages)
Specifications of MC9S12E128CPV
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
16 bit
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP-112
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
8 bit, 2 Channel
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Quantity
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Part Number:
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Chapter 4 Clocks and Reset Generator (CRGV4)
4.3.2.9
This register controls the COP (computer operating properly) watchdog.
Read: anytime
Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode
Write: RSBCK: once
178
RSBCK
CR[2:0]
Reset
WCOP
Field
2:0
7
6
W
R
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the
time-out logic restarts and the user must wait until the next window before writing to ARMCOP.
the exact duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP
counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by
periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
CRG COP Control Register (COPCTL)
0
7
= Unimplemented or Reserved
1
RSBCK
OSCCLK cycles are referenced from the previous COP time-out reset
(writing 0x0055/0x00AA to the ARMCOP register)
CR2
0
6
0
0
0
0
1
1
1
1
Figure 4-12. CRG COP Control Register (COPCTL)
Table 4-8. COPCTL Field Descriptions
CR1
0
0
1
1
0
0
1
1
Table 4-9. COP Watchdog Rates
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
CR0
0
1
0
1
0
1
0
1
0
0
4
Description
Cycles to Time Out
COP disabled
OSCCLK
0
0
3
2
2
2
2
2
2
2
14
16
18
20
22
23
24
1
CR2
0
2
Table
Freescale Semiconductor
CR1
0
1
4-9). The COP
Table 4-9
CR0
0
0
shows
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