MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 175

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

4.3.2.7
This register controls the PLL functionality.
Read: anytime
Write: refer to each bit for individual write conditions
Freescale Semiconductor
COPWAI
RTIWAI
PLLON
Reset
AUTO
Field
Field
CME
ACQ
1
0
7
6
5
4
W
R
CME
RTI Stops in Wait Mode Bit — Write: anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock
Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause
Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss
Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the
PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.
0 PLL is turned off.
1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
Automatic Bandwidth Control Bit — AUTO selects either the high bandwidth (acquisition) mode or the low
bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime
except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1.
0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit.
1 Automatic mode control is enabled and ACQ bit has no effect.
Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect.
0 Low bandwidth filter is selected.
1 High bandwidth filter is selected.
CRG PLL Control Register (PLLCTL)
1
7
mode.
unpredictable operation of the MCU.
of clock will not be detected.
= Unimplemented or Reserved
PLLON
1
6
Table 4-4. CLKSEL Field Descriptions (continued)
Figure 4-10. CRG PLL Control Register (PLLCTL)
Table 4-5. PLLCTL Field Descriptions
AUTO
MC9S12E128 Data Sheet, Rev. 1.07
1
5
ACQ
1
4
Description
Description
0
0
3
Chapter 4 Clocks and Reset Generator (CRGV4)
PRE
0
2
PCE
0
1
SCME
1
0
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