MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 168

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

Chapter 4 Clocks and Reset Generator (CRGV4)
4.2.3
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
4.3
This section provides a detailed description of all registers accessible in the CRGV4.
4.3.1
Table 4-1
168
1
2
3
CTFLG is intended for factory test purposes only.
FORBYP is intended for factory test purposes only.
CTCTL is intended for factory test purposes only.
Memory Map and Register Definition
Address
gives an overview on all CRGV4 registers.
0x000A
0x000B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Offset
RESET — Reset Pin
Module Memory Map
CRG Synthesizer Register (SYNR)
CRG Reference Divider Register (REFDV)
CRG Test Flags Register (CTFLG)
CRG Flags Register (CRGFLG)
CRG Interrupt Enable Register (CRGINT)
CRG Clock Select Register (CLKSEL)
CRG PLL Control Register (PLLCTL)
CRG RTI Control Register (RTICTL)
CRG COP Control Register (COPCTL)
CRG Force and Bypass Test Register (FORBYP)
CRG Test Control Register (CTCTL)
CRG COP Arm/Timer Reset (ARMCOP)
Figure 4-2. PLL Loop Filter Connections
MCU
MC9S12E128 Data Sheet, Rev. 1.07
Table 4-1. CRGV4 Memory Map
XFC
1
3
Use
RS
CS
2
CP
V
DDPLL
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W