MC9S12E128CPV Freescale Semiconductor, MC9S12E128CPV Datasheet - Page 349

• Manufacturer Part Number: MC9S12E128CPV
• Description: Microcontrollers (MCU) 16 Bit 16MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12E128CPV

• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-112
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• On-chip Dac: 8 bit, 2 Channel
• Lead Free Status / Rohs Status: No RoHS Version Available

11.3.2.25 PMF Enable Control B Register (PMFENCB)
Read anytime and write only if MTG is set.
Freescale Semiconductor
Module Base + 0x0028
PWMRIEB
PWMENB
LDOKB
Reset
Field
7
1
0
W
R
PWMENB
PWM Generator B Enable — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit when set enables the PWM generator B and the PWM2 and PWM3 pins. When PWMENB
is clear, PWM generator B is disabled, and the PWM2 and PWM3 pins are in their inactive states unless the
OUTCTL2 and OUTCTL3 bits are set.
0 PWM generator B and PWM2–3 pins disabled unless the respective OUTCTL bit is set.
1 PWM generator B and PWM2–3 pins enabled.
Load Okay B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit loads the PRSCB bits, the PMFMODB register and the PWMVAL2–3 registers into a set of
buffers. The buffered prescaler divisor B, PWM counter modulus B value, PWM2–3 pulse widths take effect at
the next PWM reload.
Set LDOKB by reading it when it is logic zero and then writing a logic one to it. LDOKB is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKB.
0 Do not load new modulus B, prescaler B, and PWM2–3 values.
1 Load prescaler B, modulus B, and PWM2–3 values.
Note: Do not set PWMENB bit before setting the LDOKB bit and do not clear the LDOKB bit at the same time as
PWM Reload Interrupt Enable B — If MTG is clear, this bit reads zero and cannot be written.
If MTG is set, this bit enables the PWMRFB flag to generate CPU interrupt requests.
0 PWMRFB CPU interrupt requests disabled
1 PWMRFB CPU interrupt requests enabled
0
7
setting the PWMENB bit.
= Unimplemented or Reserved
Figure 11-31. PMF Enable Control B Register (PMFENCB)
0
0
6
Table 11-32. PMFENCB Field Descriptions
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
0
0
4
Description
0
0
3
0
0
2
LDOKB
0
1
PWMRIEB
0
0
349