R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1197

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
14.5.5 Manual Reset in
Watchdog Timer Mode
15.5.3 Transition to Standby
Mode after Setting Register
15.5.4 Crystal Oscillator Circuit
for RTC
Figure 15.6 Example of
Connecting Crystal Oscillator
Circuit for RTC
16.3.6 Serial Control Register
(SCSCR)
16.3.8 Bit Rate Register
(SCBRR)
Table 16.4 Bit Rates and SCBRR
Settings (Asynchronous Mode) (2)
Table 16.4 Bit Rates and SCBRR
Settings (Asynchronous Mode) (5)
Table 16.5 Bit Rates and SCBRR
Settings (Clocked Synchronous
Mode) (1)
Item
Page
637
665
666
682
694
695
696
Revision (See Manual for Details)
Description deleted
... CPU acquires the bus mastership.
Description amended
... mode after waiting for two count clocks or more.
Figure amended
Notes: 7. When not using a crystal oscillation circuit
Table amended
Table amended
Table amended
Table amended
Bit Rate
(bit/s)
19200
Bit
3
Bit Rate
(bit/s)
4800
Bit Rate
(bit/s)
250
1 M
2 M
n
0
Bit Name
REIE
N
194
n
0
n
3
—
30
for RTC, fix the RTC_X1 pin (pull-up, pull-
down, connect to power supply, or connect
to ground) and leave the RTC_X2 pin
open.
Error
(%)
0.16
N
12
5
N
77
—
8
Initial
Value
0
Error
( )
0.16
n
0
n
3
N
214
33
R/W
R/W
n
0
Error
(%)
–0.07
8
N
124
9.8304
N
15
Description
Receive Error Interrupt Enable
Enables or disables the receive-error (ERI) interrupts
and break (BRI) interrupts. The setting of REIE bit is
valid only when RIE bit is set to 0.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Note: * ERI or BRI interrupt requests can be cleared by
(BRI) requests are disabled
(BRI) requests are enabled*
n
0
n
3
0
Error
( )
0.00
Pφ (MHz)
N
233 0.16
reading the ER, BR or ORER flag after it has
been set to 1, then clearing the flag to 0, or by
clearing RIE and REIE to 0. Even if RIE is set
to 0, when REIE is set to 1, ERI or BRI
interrupt requests are enabled.
P (MHz)
36
P (MHz)
Main Revisions for This Edition
Error
(%)
16
n
0
N
249
3
n
0
N
15
n
—
—
10
N
246
38
Error
( )
1.73
28.7
Page 1169 of 1190
N
—
—
Error
(%)
0.16
n
0
n
1
n
—
—
N
19
N
64
12
40
30
N
—
—
Error
( )
–2.34
Error
(%)
0.16