R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 61

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Addressing Mode Instruction Format
PC relative
Immediate
disp:12
Rn
#imm:20
#imm:8
#imm:8
#imm:8
#imm:3
Effective Address Calculation
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
The effective address is the sum of PC value and
Rn.
The 20-bit immediate data (imm) for the MOVI20
instruction is sign-extended.
The 20-bit immediate data (imm) for the MOVI20S
instruction is shifted by eight bits to the left, the
upper bits are sign-extended, and the lower bits
are padded with zero.
Sign-extended
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and then quadrupled.
The 3-bit immediate data (imm) for the BAND,
BOR, BXOR, BST, BLD, BSET, and BCLR
instructions indicates the target bit location.
31
extended imm (20 bits)
(sign-extended)
Sign-
31 27
imm (20 bits) 00000000
PC
Rn
disp
PC
2
19
8
×
0
+
0
+
PC + disp × 2
PC + Rn
Equation
PC + disp × 2
PC + Rn
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Section 2 CPU