R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 658

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 14 Watchdog Timer (WDT)
14.3.3
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
WRCSR is initialized to H'1F by input of a reset signal from the RES pin or in deep standby
mode, but is not initialized by the internal reset signal generated by overflow of the WDT.
WRCSR is initialized to H'1F in software standby mode.
Note: The method for writing to WRCSR differs from that for other registers to prevent
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Bit
7
6
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Watchdog Reset Control/Status Register (WRCSR)
Bit Name
WOVF
RSTE
Initial value:
Initial
Value
0
0
R/W:
Bit:
R/(W)
WOVF
0
7
R/W
R/(W)
R/W
RSTE
R/W
0
6
RSTS
R/W
Description
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
•
Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
Watchdog Timer Overflow
0
5
When 0 is written to WOVF after reading WOVF
—
1
R
4
WTCSR reset within WDT.
—
R
1
3
—
R
2
1
—
R
1
1
—
R
0
1
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010