R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 137
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R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 137 of 1222
- Download datasheet (8Mb)
SH7201 Group
5.7.2
When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU
operates as follows:
1. The exception service routine start address which corresponds to the vector number specified
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.7.3
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, an instruction that rewrites
the PC, a 32-bit instruction, an RESBANK instruction, a DIVS instruction, or a DIVU instruction,
slot illegal exception handling starts when such kind of instruction is decoded. The CPU operates
as follows:
1. The exception service routine start address is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
4. After jumping to the address fetched from the exception handling vector table, program
5.7.4
When undefined code placed anywhere other than immediately after a delayed branch instruction
(delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles
general illegal instructions in the same way as slot illegal instructions. Unlike processing of slot
illegal instructions, however, the program counter value stored is the start address of the undefined
code.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
in the TRAPA instruction is fetched from the exception handling vector table.
instruction to be executed after the TRAPA instruction.
execution starts. The jump that occurs is not a delayed branch.
delayed branch instruction immediately before the undefined code, the instruction that rewrites
the PC, the 32-bit instruction, the RESBANK instruction, the DIVS instruction, or the DIVU
instruction.
execution starts. The jump that occurs is not a delayed branch.
Trap Instructions
Slot Illegal Instructions
General Illegal Instructions
Section 5 Exception Handling
Page 109 of 1190
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