R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 816

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 18 Serial Sound Interface (SSI)
18.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to this register is transferred to the shift register upon transmission request. If the data
word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit
in SSICR. The data in the buffer can be accessed by reading this register.
SSITDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
18.3.4
SSIRDR is a 32-bit register that stores receive messages.
Data in this register is transferred from the shift register each time data word is received. If the
data word length is less than 32 bits, the alignment is determined by the setting of the PDTA
control bit in SSICR.
SSIRDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
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Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Transmit Data Register (SSITDR)
Receive Data Register (SSIRDR)
R/W
R/W
31
15
31
15
0
0
R
R
0
0
R/W
R/W
30
14
30
14
0
0
R
R
0
0
R/W
R/W
29
13
29
13
0
0
R
R
0
0
R/W
R/W
28
12
28
12
0
0
R
R
0
0
R/W
R/W
27
11
27
11
0
0
R
R
0
0
R/W
R/W
26
10
26
10
0
0
R
R
0
0
R/W
R/W
25
25
R
R
0
9
0
0
9
0
R/W
R/W
24
24
0
8
0
R
R
0
0
8
R/W
R/W
23
23
0
7
0
R
R
0
7
0
R/W
R/W
22
22
0
6
0
R
R
0
6
0
R/W
R/W
21
21
0
5
0
R
R
0
5
0
R/W
R/W
20
20
R
R
0
4
0
0
4
0
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
19
19
R
R
0
3
0
0
3
0
R/W
R/W
18
18
R
R
0
2
0
0
2
0
SH7201 Group
R/W
R/W
17
17
Sep 24, 2010
R
R
0
1
0
0
1
0
R/W
R/W
16
16
R
R
0
0
0
0
0
0