R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 277

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0.
(4)
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh
control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place
simultaneously for all channels.
An auto-refresh cycle operation takes place immediately before transition to self-refresh mode.
While in self-refresh mode the CKE signal is low level. Immediately after recovery from self-
refresh mode an auto-refresh cycle is triggered.
Figure 9.7 shows the timing of transition to self-refresh mode, and figure 9.8 shows the timing of
recovery from self-refresh mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Function/Operation
Mode register settings
Clock stop control signal
settings
Self-Refresh
2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have
been cleared to 0 before rewriting this bit.
Figure 9.7 Example of Timing of Transition to Self-Refresh Mode
CKIO
SDRAM command
Register
SD0MOD,
SD1MOD*
SDCKSCNT
(DREFW Bit Set Value: 0010)
DSL: Deselect command
RFA: Auto-refresh command
RFS: Self-refresh entry command
2
Auto-refresh cycle
RFA
DREFW
Conditions
•
•
•
•
•
DSL
SDRAM access disabled (set in SDRAMCm*
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
DSL
Self-refresh mode (CKE = L)
RFS
Section 9 Bus State Controller (BSC)
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