R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 630

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 13 8-Bit Timers (TMR)
13.3.1
TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in
TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an
external reset input signal, compare match A signal, or compare match B signal. Which signal is to
be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from
H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. The value in TCORA is
continually compared with the value in TCNT. When a match is detected, the corresponding
CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a
TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare
match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is
initialized to H'FF.
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Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Timer Counter (TCNT)
Time Constant Register A (TCORA)
R/W
R/W
0
1
7
7
R/W
R/W
0
1
6
6
R/W
R/W
0
1
5
5
R/W
R/W
TCORA_0
TCNT_0
0
1
4
4
R/W
R/W
0
3
3
1
R/W
R/W
0
2
2
1
R/W
R/W
1
0
1
1
R/W
R/W
1
0
0
0
R/W
R/W
0
1
7
7
R/W
R/W
0
1
6
6
R/W
R/W
0
1
5
5
R/W
R/W
TCORA_1
TCNT_1
0
1
4
4
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
0
3
3
1
R/W
R/W
0
2
2
1
SH7201 Group
R/W
R/W
Sep 24, 2010
1
0
1
1
R/W
R/W
1
0
0
0