R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1217

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
SCIF module timing ............................. 1141
Searching cache ...................................... 189
Sending a break signal ............................ 727
Serial communication interface
with FIFO (SCIF) ................................... 669
Serial sound interface (SSI) .................... 773
Setting analog input voltage ........... 899, 908
Shift instructions....................................... 52
Sign extension of word data...................... 26
Single mode ............................................ 886
Slave receive operation........................... 756
Slave transmit operation ......................... 753
Sleep mode ........................................... 1008
Slot illegal instructions ........................... 109
Software standby mode......................... 1009
Stack after interrupt
exception handling.................................. 148
Stack status after exception
handling ends .......................................... 112
Standby control circuit.............................. 75
Status register (SR) ................................... 20
System control instructions....................... 54
T
T bit .......................................................... 28
TAP controller ...................................... 1023
Test mode settings .................................. 863
Time quanta is defined............................ 834
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Timing to clear an interrupt source ......... 160
Transfer rate ............................................ 735
Trap instructions ..................................... 109
Types of exception handling and
priority order ............................................. 91
U
UBC trigger timing ............................... 1137
UDTDO output timing .......................... 1024
Unconditional branch instructions
with no delay slot ...................................... 27
User break controller (UBC)................... 161
User break interrupt ................................ 133
User debugging interface (H-UDI) ....... 1019
Using interval timer mode....................... 635
Using watchdog timer mode ................... 634
V
Vector base register (VBR)....................... 22
W
Watchdog timer (WDT) .......................... 625
Watchdog timer timing ......................... 1140
Write-Back Buffer
(Only for Operand Cache)....................... 192
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