R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 769
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 769 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
4
3
2
1
0
Bit Name
NAKIE
STIE
ACKE
ACKBR
ACKBT
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
Description
NACK Receive Interrupt Enable
Enables or disables the NACK detection, arbitration lost
and overrun error interrupt request (NAKI) when the
NACKF or AL/OVE bit in ICSR is set. NAKI can be
canceled by clearing the NACKF, AL/OVE, or NAKIE bit
to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Stop Condition Detection Interrupt Enable
Enables or disables the stop condition detection
interrupt request (STPI) when the STOP bit in ICSR is
set.
0: Stop condition detection interrupt request (STPI) is
1: Stop condition detection interrupt request (STPI) is
Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
1: If the receive acknowledge bit is 1, continuous
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified. This bit can be canceled by setting the
BBSY bit in ICCR2 to 1.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
disabled.
enabled.
and continuous transfer is performed.
transfer is halted.
Section 17 I
2
C Bus Interface 3 (IIC3)
Page 741 of 1190
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