R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 212

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 8 Cache
8.2
The cache has the following registers.
Table 8.2
8.2.1
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode
or write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in an address space that is not
cached, and an address space that is cached should be accessed after reading the contents of
CCR1.
CCR1 is initialized to H'00000000 by a power-on reset and in deep standby but not initialized by a
manual reset or in software standby mode.
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Register Name
Cache control register 1
Cache control register 2
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Register Descriptions
Cache Control Register 1 (CCR1)
31
15
R
R
0
0
Register Configuration
30
14
R
R
0
0
29
13
R
R
0
0
28
12
R
R
Abbreviation
CCR1
CCR2
0
0
R/W
ICF
27
11
R
0
0
26
10
R
R
0
0
25
R
R
R/W
R/W
R/W
0
9
0
R/W
ICE
24
R
0
8
0
Initial Value
H'00000000
H'00000000
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
Address
H'FFFC1000 32
H'FFFC1004 32
20
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
OCF
R/W
19
R
0
3
0
18
R
R
0
2
0
Access Size
SH7201 Group
R/W
WT
17
Sep 24, 2010
R
0
1
0
OCE
R/W
16
R
0
0
0