R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 750

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Clocked Synchronous Mode)
Figures 16.13 and 16.14 show sample flowcharts for receiving serial data. When switching from
asynchronous mode to clocked synchronous mode without SCIF initialization, make sure that
ORER, PER, and FER are cleared to 0.
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No
No
Figure 16.13 Sample Flowchart for Receiving Serial Data (1)
Figure 16.14 Sample Flowchart for Receiving Serial Data (2)
Clear RE bit in SCSCR to 0
Read ORER flag in SCLSR
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Read receive data in
flag in SCFSR to 0
All data received?
Start of reception
End of reception
ORER = 1?
RDF = 1?
No
Yes
Yes
No
Clear ORER flag in SCLSR to 0
Error handling
[2]
[3]
Overrun error handling
Yes
Error handling
ORER = 1?
[1]
End
Yes
[1] Receive error handling:
[2] SCIF status check and receive data read:
[3] Serial reception continuation procedure:
Read the ORER flag in SCLSR to identify
any error, perform the appropriate error
handling, then clear the ORER flag to 0.
Reception cannot be resumed while the
ORER flag is set to 1.
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, read at least
the receive trigger set number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFRDR. However, the RDF bit is
cleared to 0 automatically when an RXI
interrupt activates the DMAC to read the
data in SCFRDR.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010