R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 363

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
11.3.13 DMA Interrupt Status Register (DMISTS)
DMISTS consists of the DMA interrupt request status bits.
Notes: 1. This register is read-only.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 24 DISTS
23 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
Bit Name
⎯
1, …, 24: channel 7).
31
15
—
R
R
0
0
30
14
—
R
R
0
0
29
13
—
R
R
0
0
Initial
Value
All 0
All 0
28
12
—
R
R
0
0
DISTS
27
11
—
R
R
0
0
R/W
R
R
26
10
—
R
R
0
0
Description
DMA Interrupt Request Status
These bits are used to verify the sources of common
interrupt requests for the interrupt controller.
•
•
0: No interrupt request
1: An interrupt request exists
Reserved
These bits are always read as 0. The write value
should always be 0.
25
—
R
R
0
9
0
Condition for setting to "1"
When the DMA common interrupt request signal
control bit (DINTA) for a channel is set to "1" and
the DMA transfer end condition is detected, the
corresponding bit is set to "1". The setting of the
DMA interrupt control bit (DINTM) does not affect
this setting.
Condition for clearing to "0"
A DISTS bit is cleared to "0" by clearing the
corresponding DMA transfer end condition
detection bit (DEDET) in the DMA transfer end
detection register (DMEDET). For details, see
section 11.5.2, DMA Interrupt Requests.
24
—
R
R
0
8
0
23
—
—
R
R
0
7
0
Section 11 Direct Memory Access Controller (DMAC)
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
Page 335 of 1190
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0