R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 136

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 5 Exception Handling
5.7
5.7.1
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Page 108 of 1190
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
FPU exceptions
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Undefined code anywhere
besides in a delay slot
Division by zero
Negative maximum value ÷ (−1)
Instructions that cause disabled
operation exception defined by
IEEE754 standard or division
exception by zero. Instructions
that could cause overflow,
underflow, or imprecise
exception.
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
DIVU, DIVS
DIVS
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010