R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 789

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
17.4.7
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 17.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
SCL or SDA
input signal
Sampling
clock
Noise Filter
D
Sampling clock
Peripheral clock
Latch
C
cycle
Figure 17.17 Block Diagram of Noise Filter
Q
D
Latch
C
Q
D
Latch
C
NF2CYC
Q
detector
detector
Match
Match
Section 17 I
2
1
0
C Bus Interface 3 (IIC3)
Page 761 of 1190
Internal
SCL or SDA
signal