R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 33
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 33 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Item
Direct memory access
controller (DMAC)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Features
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Eight channels; external request available for four of them
Can be activated by software, on-chip modules, or external devices
⎯ Software; 1, internal source; 32, external source; 4
Up to 64 Mbytes can be transferred
Maximum transfer data size
⎯ 8, 16, or 32 bits for single-data transfer
⎯ 1, 2, 4, 8, 16, 32, 64, or 128 sets of data for single operand transfer
Transfer method
⎯ Cycle-stealing transfer (dual address transfer)
⎯ Pipeline transfer (dual address transfer)
Addressing method
Increment, decrement, or fixed
Three clock cycles per one set of data (best)
Transfer modes
Single operand transfer, continuous operand transfer, and non-stop
transfer
An interrupt is requested when the byte count reaches 0
Reloading function
Source address, destination address, and byte count
DMAC suspend, resume, and stop function
DMAC forcible terminate function
Clock mode: Input clock can be selected from external input (EXTAL
or CKIO) or crystal resonator
Input clock can be multiplied by 16 (max.) by the internal PLL circuit
Three types of clocks generated
CPU clock: Maximum 120 MHz
Bus clock: Maximum 60 MHz
Peripheral clock: Maximum 40 MHz
On-chip one-channel watchdog timer
A counter overflow can reset this LSI
(a transfer continues until the byte count reaches 0)
Three clock cycles per one set of data (best)
Bus released between read and write cycles
One clock cycle per one set of data (best)
Section 1 Overview
Page 5 of 1190
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