R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 321

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
10.2
The bus monitor function detects two types of bus error: illegal address access and bus timeout.
Bus error detection is performed in one bus access.
Even when data is transferred in multiple bus accesses such as burst transfer, a bus error can be
detected in one bus access.
10.2.1
When a bus error is detected, the status is saved in the bus monitor status register 1 (SYCBESTS1)
and bus monitor status register 2 (SYCBESTS2) and the CPU is notified of the bus error is
notified to the CPU.
(1)
When a bus error occurs, the status at the time (what type of error occurred and which bus was
being accessed by which bus master) is saved in the bus monitor status register 1 (SYCBESTS1)
or bus monitor status register 2 (SYCBESTS2).
Even if another bus error occurs after this, the value in the bus monitor status register
(SYCBESTS) or bus monitor status register 2 (SYCBESTS2) is not updated. When multiple bus
errors occur at the same time, multiple status bits may be set.
The bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2)
can be cleared by writing 1 to the status clear bit (STSCLR) in the bus monitor enable register
(SYCBEEN) from the bus master. After being cleared, the status of a bus error, if generated, is
saved in the bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2
(SYCBESTS2) again.
When a clear operation and a bus error happen at the same time, the clear operation has priority
and the bus error is ignored.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Saving Status in Bus Monitor Status Register or Bus Monitor Status Register 2
Bus Monitor Function
Operation when a Bus Error is Detected
Section 10 Bus Monitor
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