R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 192

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 7 User Break Controller (UBC)
7.3.1
BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in
each channel. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the
three address buses for a break condition. BAR is initialized to H'00000000 by a power-on reset or
in deep standby, but retains its previous value by a manual reset or in software standby mode or
sleep mode.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR to 0.
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Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Break Address Register (BAR)
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
BA15 BA14 BA13 BA12 BA11 BA10 BA9
Bit Name
BA31 to BA0 All 0
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Break Address
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions.
When the C bus and instruction fetch cycle are
selected by BBR, specify an FAB address in bits BA31
to BA0.
When the C bus and data access cycle are selected by
BBR, specify an MAB address in bits BA31 to BA0.
R/W
R/W
25
0
9
0
R/W
R/W
BA8
24
0
8
0
R/W
R/W
BA7
23
0
7
0
R/W
R/W
BA6
22
0
6
0
R/W
R/W
BA5
21
0
5
0
R/W
R/W
BA4
20
0
4
0
R01UH0026EJ0300 Rev. 3.00
R/W
R/W
BA3
19
0
3
0
R/W
R/W
BA2
18
0
2
0
SH7201 Group
R/W
R/W
BA1
17
Sep 24, 2010
0
1
0
R/W
R/W
BA0
16
0
0
0