R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 815

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
1
0
2. The SSI clock must be kept supplied until the SSI is in the idle state.
Bit Name
SWNO
IDST
ignored.
Initial
Value
1
1*
2
R
R/W
R
Description
System Word Number
This status bit indicates the current word number.
•
•
Idle Mode Status Flag
This status flag indicates that the serial bus activity has
stopped.
This bit is cleared if EN = 1 and the serial bus are
currently active.
This bit is automatically set to 1 under the following
conditions.
•
•
•
Note: If the external master stops the serial bus clock
TRMD = 0 (Receive mode)
SWNO indicates which system word the data in
SSIRDR currently represents. This value will
change as the data in SSIRDR is updated from the
shift register, regardless of whether SSIRDR has
been read.
TRMD = 1 (Transmit mode)
SWNO indicates which system word is required to
be written to SSITDR. This value will change as the
data is copied to the shift register, regardless of
whether the data is written to SSITDR.
SSI = Master transmitter (SWSD = 1 and
TRMD = 1)
This bit is set to 1 if the EN bit is cleared and the
data written to SSITDR is completely output from
the serial data input/output pin (SSIDATA), that is,
the output of the system word length is completed.
SSI = Master receiver (SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
SSI = Slave transmitter/receiver (SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
before the current system word is completed,
this bit is not set.
Section 18 Serial Sound Interface (SSI)
Page 787 of 1190