EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 109

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–3. RCLK Networks in Arria II GX Devices
Notes to
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) RCLK[0..5] is not driven by any clock pins because there are no dedicated clock pins on the left side of the Arria II GX devices.
Figure 5–4. RCLK Networks in Arria II GZ Devices
Note to
(1) A maximum of four signals from the core can drive into each group of RCLKs. For example, only four core signals can drive into RCLK[0..5] and
December 2010 Altera Corporation
another four core signals can drive into RCLK[54..63] at any one time.
Figure
Figure
5–4:
5–3:
Top Left PLL
Bottom Left PLL
CLK[0..3]
PLL_1
PLL_4
L2
L3
RCLK[6..11]
RCLK[0..5]
(2)
RCLK[6..11]
(2)
RCLK[0..5]
RCLK[42..47]
RCLK[12..17]
(Note 1)
RCLK[12..21] RCLK[22..31]
RCLK[54..63] RCLK[44..53]
CLK[4..7]
CLK[12..15]
Q1
Q4
Q1
Q4
CLK[12..15]
CLK[4..7]
T1
B1
RCLK[18..23]
Q2
Q3
Q2
Q3
B2
T2
RCLK[36..41]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
RCLK[24..29]
RCLK[30..35]
RCLK[38..43]
RCLK[32..37]
Bottom Right PLL
PLL_2
PLL_3
PLL_5
PLL_6
Top Right PLL
R2
R3
(1)
(1)
CLK[8..11]
Center PLLs
CLK[8..11]
5–5