EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 119

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
December 2010 Altera Corporation
f
For more information, refer to the
User
Figure 5–9
Figure 5–9. RCLK Control Block for Arria II GX Devices
Note to
(1) This clock select signal can only be statically controlled through a configuration file (.sof or .pof) and cannot be
Figure 5–10. RCLK Control Block for Arria II GZ Devices
Notes to
(1) When the device is in user mode, you can only set the clock select signals through a configuration file
(2) The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input.
dynamically controlled during user mode operation.
(.sof or .pof). You cannot dynamically control the clock.
Guide.
Figure
Figure
and
5–9:
5–10:
Figure 5–10
PLL Counter
Outputs
PLL Counter
Outputs
show the RCLK select blocks.
2
Clock Control Block (ALTCLKCTRL) Megafunction
2
CLK
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Pin
Enable/
CLKp
Disable
RCLK
Pin
Enable/
Disable
RCLK
CLKn
Pin
(2)
Internal
Logic
Internal
Static Clock Select (1)
Logic
Internal
Static Clock Select (1)
Logic
Internal
Logic
5–15