EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 361

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX51011-4.0
BST Architecture for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51011-4.0
IEEE Std. 1149.6 Boundary-Scan Register for Arria II GX Devices
f
This chapter describes the boundary-scan test (BST) features that are supported in
Arria
Arria II devices. The features are similar to Arria GX devices, unless stated in this
chapter.
This chapter includes the following sections:
■
■
■
■
■
Arria II GX devices support IEEE Std. 1149.1 and IEEE Std. 1149.6, while Arria II GZ
devices support IEEE Std. 1149.1 only. The IEEE Std. 1149.6 is only supported on the
high-speed serial interface (HSSI) transceivers in Arria II GX devices. The IEEE Std.
1149.6 enables board-level connectivity checking between transmitters and receivers
that are AC coupled (connected with a capacitor in series between the source and
destination).
For Arria II GX devices, the TDO output pin and all JTAG input pins are powered by
the V
pin and all the JTAG input pins are powered by 2.5-V/3.0-V V
Bank 1A. All user I/O pins are tri-stated during JTAG configuration.
For more information about the IEEE Std. 1149.1 BST architecture, BST circuitry, and
boundary-scan register for Arria II devices, refer to the
Boundary-Scan Testing for Arria GX Devices
Handbook.
The boundary-scan cell (BSC) for HSSI transmitters (GXB_TX[p,n]) and
receivers/input clock buffer (GXB_RX[p,n])/(REFCLK[0..7]) in Arria II GX devices are
different from the BSCs for I/O pins.
“BST Architecture for Arria II Devices” on page 11–1
“BST Operation Control” on page 11–3
“I/O Voltage Support in a JTAG Chain” on page 11–5
“Disabling IEEE Std. 1149.1 BST Circuitry” on page 11–6
“Boundary-Scan Description Language Support” on page 11–7
®
CCIO
II devices and how to use the IEEE Std. 1149.1 and Std. 1149.6 BST circuitries in
power supply of I/O Bank 8C, while for Arria II GZ devices, the TDO output
11. JTAG Boundary-Scan Testing in
chapter in volume 2 of the Arria GX Device
IEEE 1149.1 (JTAG)
Arria II Devices
CCPD
supply of I/O
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