EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 551

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric PLL-Transceiver PLL Cascading
Figure 2–35. FPGA Fabric PLLs-Transceiver PLLs Cascading Options Allowed for 1152-Pin Package Devices
December 2010 Altera Corporation
Dedicated Left and Right PLL Cascade Network in Arria II GZ Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 780-Pin Package
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 1152-Pin Package
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Arria II GZ devices have a dedicated PLL cascade network on the left and right side of
the device that connects to the input reference clock selection multiplexer of the CMU
PLLs, and receiver CDRs on the left and right side of the device.
The dedicated PLL cascade networks are segmented by bidirectional tri-state buffers
located along the clock line. Segmentation of the dedicated PLL cascade network
allows two or more left and right PLLs to drive the cascade clock line simultaneously.
Because the number of left and right PLLs and transceiver blocks vary from device to
device, the capability of cascading a left and right PLL to the CMU PLLs, and receiver
CDRs also varies from device to device.
The following sections describe the Arria II GZ FPGA fabric-transceiver PLL’s
cascading for the various device packages.
Arria II GZ devices in 780-pin packages do not support FPGA fabric PLLs-transceiver
PLL’s cascading.
Figure 2–35
in the EP2AGZ300H29, EP2AGZ350H29, EP2AGZ225FF35, EP2AGZ300FF35, and
EP2AGZ350FF35 devices.
CMU1
CMU0
CMU0
CDR
CMU1
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
Cascade
Network
shows the FPGA fabric PLLs-transceiver PLL’s cascading options allowed
PLL
PLL_L2
EP2AGZ300H29
EP2AGZ350H29
EP2AGZ225F35
EP2AGZ300F35
EP2AGZ350F35
PLL_R2
Cascade
Network
PLL
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBR1
Transceiver Block GXBR0
CMU1
CMU0
CDR
CMU0
CDR
CDR
CMU1
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
Channel 3
Channel 0
Channel 0
Channel 3
Channel 2
Channel 1
Channel 2
Channel 1
2–61