EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 164

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–6
Figure 6–2. I/O Banks in Arria II GZ Devices
Notes to
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without R
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
(5) Clock inputs on column I/Os are powered by V
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
inverted.
single-ended clock inputs. All outputs use the corresponding bank V
Figure 6–2
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
6–2:
Bank 3A
Bank 8A
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation.
Arria II GZ devices contain up to 20 I/O banks as shown in
can support high-performance external memory interfaces with dedicated circuitry.
The I/O pins are organized in pairs to support differential standards. Each I/O pin
pair can support both differential input and output buffers except the clk[1,3,8,10],
PLL_L[1,4]_clk, and PLL_R[1,4]_clk pins, which support differential input
operations only.
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation.
Bank 3B
Bank 8B
CCCLKIN
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-
V, 1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I
& II, SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15
Class I, HSTL-12 Class I, LVDS, RSDS, mini-LVDS,
differential SSTL-2 Class I & II, differential SSTL-18
Class I & II, differential SSTL-15 Class I, differential
HSTL-18 Class I & II, differential HSTL-15 Class I and
differential HSTL-12 Class I standards for input and
output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations
(Note
when configured as differential clock inputs. They are powered by V
1), (2), (3), (4), (5), (6), (7),
Bank 8C
Bank 3C
CCIO
.
Bank 7C
Bank 4C
D
OCT support.
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation.
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation.
(8)
Chapter 6: I/O Features in Arria II Devices
Bank 7B
Bank 4B
Figure
December 2010 Altera Corporation
6–2. Each I/O bank
CCIO
Bank 7A
Bank 4A
when configured as
I/O Banks