EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 197

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX51007-4.0
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51007-4.0
f
f
1
1
This chapter describes the hardware features in Arria
high-speed memory interfacing for the double data rate (DDR) memory standard
including delay-locked loops (DLLs). Memory interfaces also use I/O features such as
on-chip termination (OCT), programmable input delay chains, programmable output
delay, slew rate adjustment, and programmable drive strength.
Arria II devices provide an efficient architecture to quickly and easily fit wide external
memory interfaces with their small modular I/O bank structure. The I/Os are
designed to provide flexible and high-performance support for existing and emerging
external DDR memory standards, such as DDR3, DDR2, DDR SDRAM, QDR II,
QDR II+ SRAM, and RLDRAM II. The Arria II FPGA supports DDR external memory
on the top, bottom, left, and right I/O banks.
The high-performance memory interface solution includes the self-calibrating
ALTMEMPHY megafunction and UniPHY Intellectual Property (IP) core, optimized
to take advantage of the Arria II I/O structure and the Quartus
Analyzer. The ALTMEMPHY megafunction and UniPHY IP core provide the total
solution for the highest reliable frequency of operation across process, voltage, and
temperature (PVT) variations.
The ALTMEMPHY megafunction and UniPHY IP core instantiate a phase-locked loop
(PLL) and PLL reconfiguration logic to adjust the resynchronization phase shift based
on PVT variation.
This chapter includes the following sections:
■
■
■
Arria II GZ devices only support the UniPHY IP core. Arria II GX devices support the
QDR II and QDR II + SRAM controller with the UniPHY IP core, and DDR3, DDR2,
and the DDR SDRAM controller with the ALTMEMPHY megafunction.
RLDRAM II is only available in Arria II GZ devices.
For more information about any of the above-mentioned features, refer to the
Features in Arria II Devices
For more information about external memory system specifications, implementation,
board guidelines, timing analysis, simulation, debug information, ALTMEMPHY
megafunction and UniPHY IP core support for Arria II devices, refer to the
Memory Interface
“Memory Interfaces Pin Support for Arria II Devices” on page 7–3
“Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–21
“Arria II External Memory Interface Features” on page 7–24
Handbook.
7. External Memory Interfaces in Arria II
or the
Clock Networks and PLLs in Arria II Devices
®
II devices that facilitate
®
II TimeQuest Timing
Devices
chapter.
External
I/O
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