EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 122

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–18
Figure 5–14. Clock Input Multiplexer Logic for Arria II GX PLLs
Notes to
(1) Input clock multiplexing is controlled through a configuration file (.sof or .pof) only; it cannot be dynamically controlled when the device is
(2) Dedicated clock input pins to the PLLs: n=4 for PLL_4; n=4 or 8 for PLL_3; n=8 or 12 for PLL_2; and n=12 for PLL_1.
(3) You can drive the GCLK or RCLK clock input with an output from another PLL, a pin-driven GCLK or RCLK, or through a clock control block,
Figure 5–15. Clock Input Multiplexer Logic for Arria II GZ devices
Notes to
(1) When the device is operating in user mode, input clock multiplexing is controlled through a configuration file
(2) n=0 for L2 and L3 PLLs; n=4 for B1 and B2 PLLs; n=8 for R2 and R3 PLLs, and n=12 for T1 and T2 PLLs.
(3) You can drive the GCLK or RCLK input using an output from another PLL, a pin-driven GCLK or RCLK, or through a clock control block provided
Arria II Device Handbook Volume 1: Device Interfaces and Integration
operating in user mode.
provided the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK or RCLK. An internally generated global
signal or general purpose I/O pin cannot drive the PLL.
(.sof or .pof) only and cannot be dynamically controlled.
the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK or RCLK. An internally generated global signal or
general purpose I/O pin cannot drive the PLL.
Figure
Figure
5–14:
5–15:
f
GCLK / RCLK input (3)
For more information about the clock control block and its supported features in the
Quartus II software, refer to the
Guide.
Adjacent PLL output
GCLK / RCLK input (3)
Adjacent PLL output
CLK[n+3..n] (2)
clk[n+3..n] (2)
4
4
4
4
Clock Control Block (ALTCLKCTRL) Megafunction User
(1)
(1)
(1)
(1)
inclk0
inclk1
inclk0
inclk1
Chapter 5: Clock Networks and PLLs in Arria II Devices
To the clock
switchover block
To the clock
switchover block
December 2010 Altera Corporation
Clock Networks in Arria II Devices