EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 123

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
PLLs in Arria II Devices
December 2010 Altera Corporation
Cascading PLLs
f
f
1
1
You can cascade the corner and center PLLs through the GCLK and RCLK networks
(Arria II GX devices) or left/right and top/bottom PLLs through the GCLK and
RCLK networks (Arria II GZ devices). In addition, where two PLLs exist next to each
other, there is a direct connection between them that does not require the GCLK and
RCLK network. By cascading PLLs, you can use this path to reduce clock jitter. For
Arria II GX devices, the direct PLL cascading feature is available in PLL_5 and PLL_6
on the right side of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
Arria II GX devices allow cascading of PLL_1 and PLL_4 to the transceiver PLLs (clock
management unit PLLs and receiver clock data recoveries [CDRs]). Arria II GZ
devices allows cascading the left and right PLLs to transceiver PLLs (CMU PLLs and
receiver CDRs).
If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth
setting, while the destination (downstream) PLL must have a high-bandwidth setting.
Ensure that there is no overlap of the bandwidth ranges of the two PLLs.
For more information, refer to the “FPGA Fabric PLLs-Transceiver PLLs Cascading”
section in the
For more information about PLL cascading in external memory interfaces designs,
refer to the
Guide.
Arria II GX devices offer up to six PLLs per device and seven outputs per PLL, while
Arria II GZ devices offer up to eight PLLs that provide robust clock management and
synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical
location in the device floor plan. For the location and number of PLLs in Arria II
devices, refer to
Depending on the package, Arria II GX devices offer up to eight transceiver
transmitter (TX) PLLs per device that can be used by the FPGA fabric if they are not
used by the transceiver.
For more information about the number of general-purpose and transceiver TX PLLs
in each device density, refer to the
information about using the transceiver TX PLLs in the transceiver block, refer to the
Transceiver Clocking in Arria II Devices
All Arria II PLLs have the same core analog structure and support features with
minor differences in the features that are supported for Arria II GZ devices.
External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Transceiver Clocking in Arria II Devices
Figure 5–1 on page 5–3
Overview for Arria II Device Family
Arria II Device Handbook Volume 1: Device Interfaces and Integration
chapter.
through
Figure 5–4 on page
chapter.
chapter. For more
5–5.
5–19