EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 262

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–22
Figure 8–18. LVDS and DPA Clock Networks in the Arria II GX Devices with Center PLLs
Figure 8–19. LVDS/DPA Clocks in the Arria II GZ Devices with Center PLLs
Arria II Device Handbook Volume 1: Device Interfaces and Integration
4
4
clock networks on the
left side of the device
No LVDS and DPA
4
2
2
4
The Arria II GZ have left and right PLLs that feed into the differential transmitter and
receive channels through the LVDS and DPA clock network. The center left and right
PLLs can clock the transmitter and receive channels above and below them.
Figure 8–19
For more information about Arria II devices PLL clocking restrictions, refer to
“Differential Pin Placement Guidelines” on page
LVDS
LVDS
Clock
Clock
PLL_L2
PLL_L3
Center
Center
Clock
Clock
DPA
DPA
shows center PLL clocking in the Arria II GZ devices.
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Quadrant
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Quadrant
Quadrant
Clock
Clock
DPA
DPA
8–27.
Corner
Center
Center
Corner
PLL
PLL
PLL
PLL
LVDS
LVDS
Clock
Clock
Clock
Clock
DPA
DPA
PLL_R2
PLL_R3
Center
Center
4
4
8
8
4
4
December 2010 Altera Corporation
LVDS
Clock
LVDS
Clock
LVDS and DPA Clock Networks
4
4
4
2
2
4
4
4