EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 461

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–71. Serial RapidIO Mode Datapath
Notes to
(1) This allows the fabric-to-transceiver interface to run below the maximum interface frequency and is always enabled for Serial RapidIO functional
(2) The word aligner uses the automatic synchronization state machine (10 bit /K28.5/) and is compliant with the Serial RapidIO protocol.
(3) This module is optional.
(4) This can run at 1.25, 2.5, or 3.125 Gbps.
(5) This is running at half the rate of the data rate.
(6) This is running at 62.5 MHz for 1.25 Gbps data rate, 125 MHz for 2.5 Gbps data rate, or 156.25 MHz for 3.125 Gbps data rate.
December 2010 Altera Corporation
Fabric
FPGA
mode.
Figure
1–71:
1
16-Bit Interface
Figure 1–71
RapidIO mode.
In Serial RapidIO mode, the ALTGX MegaWizard Plug-In Manager automatically
defaults the synchronization state machine to indicate synchronization (a high logic
level on the rx_syncstatus port) when the receiver acquires 127 K28.5 (10'b0101111100
or 10'b1010000011) synchronization code groups without receiving an intermediate
invalid code group. When synchronized, the state machine indicates loss of
synchronization (a low logic level on the rx_syncstatus port) when it detects three
invalid code groups separated by less than 255 valid code groups, or when it is reset.
Serial RapidIO only allows one insertion or deletion of the skip character /R/from the
/K/, /R/, /R/, /R/ clock compensation sequence. However, the Arria II GX and GZ
rate match FIFO may perform multiple insertions or deletions if the PPM difference is
more than the ±200 PPM range. Ensure that the PPM difference in your system is less
than ±200 ppm.
(6)
(6)
(6)
tx_clkout[0]
Compensation
wrclk
shows the ALTGX transceiver datapath when configured in Serial
TX Phase
FIFO
rdclk
/2
wrclk
Byte Serializer
(1)
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B/10B Encoder
Low-Speed Parallel Clock (6)
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock (6)
Parallel Recovery Clock (6)
Interface
10-Bit
Transmitter Channel
Receiver Channel
Local Divider
Clock
PMA
PMA
(5)
1–75