EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 320

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–40
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 1 of 4)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
VCCPD
nIO_PULLUP
MSEL[2..0]
MSEL[3..0]
nCONFIG
Pin Name
User Mode
N/A
N/A
N/A
N/A
N/A
Table 9–16
properly on your board for successful configuration. Some of these pins may not be
required for your configuration schemes.
Configuration
Scheme
lists the dedicated configuration pins. You must connect these pins
All
All
All
All
All
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Power
Pin Type
Input
Input
Input
Input
(1)
Dedicated power pin. Use this pin to power the I/O
pre-drivers, the HSTL/SSTL input buffers, and the
MSEL[3..0] pins.
You must connect V
in the same bank:
■
■
■
V
(for standard POR) or 4 ms (for fast POR). If V
ramped up in this specified time, your Arria II device is not
successfully configured.
Dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose I/O pins
(DATA[7..0], CLKUSR, INIT_DONE, DEV_OE, and
DEV_CLRn) are on or off before and during configuration. A
logic high turns off the weak internal pull-up resistors; a
logic low turns them on.
The nIO-PULLUP input buffer is powered by V
internal 5-kΩ pull-down resistor that is always active. You
can tie the nIO-PULLUP directly to the V
for Arria II GZ devices and the V
Arria II GX devices, or GND.
Three-bit configuration input that sets the Arria II GZ device
configuration scheme. For more information about the
appropriate connections, refer to
You must hardwire these pins to V
The MSEL[2..0] pins have internal 5-kΩ pull-down
resistors that are always active.
Four-bit configuration input that sets the Arria II GX device
configuration scheme. For more information about the
appropriate connections, refer to
You must hardwire these pins to V
The MSEL[3..0] pins have internal 5-kΩ pull-down
resistors that are always active.
Configuration control input. Pulling this pin low during
user-mode causes the device to lose its configuration data,
enter a reset state, and tri-state all I/O pins. Returning this
pin to a logic-high level starts a reconfiguration.
Configuration is possible only if this pin is high, except in
JTAG programming mode, when nCONFIG is ignored.
CCPD
For 3.3-V I/O standards, connect V
For 3.0-V I/O standards, connect V
For 2.5-V and below I/O standards, connect V
must ramp up from 0 V to 2.5, 3.0, or 3.3 V in 100 ms
CCPD
Description
according to the I/O standard used
December 2010 Altera Corporation
CCIO
Table 9–7 on page
Table 9–6 on page
CCPGM
CCPD
power supply for
CCPD
CCPD
or GND.
Device Configuration Pins
CCPGM
or GND.
to 3.3 V
to 3.0 V
CC
power supply
CCPD
CCPD
and has an
is not
9–10.
9–9.
to 2.5 V