EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 493

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
CMU PLL and Receiver CDR Input Reference Clocking
Figure 2–2. Input Reference Clock Sources Across Transceiver Blocks
December 2010 Altera Corporation
refclk0
refclk1
refclk0
refclk1
refclk0
refclk1
refclk0
refclk1
1
Figure 2–2
in four transceiver blocks on the left side of the EP2AGX260FF35 device.
refclk0 and refclk1 Pins
Each transceiver block has two dedicated refclk pins that you can use to drive the
CMU PLL, receiver CDR, input reference clock, or all three. Each of the two CMU
PLLs and four receiver CDRs within a transceiver block can derive its input reference
clock from either the refclk0 or refclk1 pin.
The refclk pins provide the cleanest input reference clock path to the CMU PLLs.
Altera recommends using the refclk pins to drive the CMU PLL input reference clock
for improved transmitter output jitter performance.
/2
/2
/2
/2
/2
/2
/2
/2
shows the input reference clock sources for CMU PLLs and receiver CDRs
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
6
6
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
and
and
and
and
2–3