EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 497

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
In non-bonded channel configurations, the high-speed serial clock and low-speed
parallel clock in each channel are generated independently by its local clock divider,
as shown in
skew. The transmitter phase compensation FIFO in each non-bonded channel has its
own pointers and control logic that can result in unequal latency in the transmitter
phase compensation FIFO of each channel. The higher transceiver clock skew and
unequal latency in the transmitter phase compensation FIFO in each channel can
result in higher channel-to-channel skew in non-bonded channel configurations.
In bonded channel configurations, the high-speed serial clock and low-speed parallel
clock for all bonded channels are generated by the same CMU0 clock divider block
(refer to
The transmitter phase compensation FIFO in all bonded channels share common
pointers and control logic generated in the CMU0 channel, resulting in equal latency in
the transmitter phase compensation FIFO of all bonded channels. The lower
transceiver clock skew and equal latency in the transmitter phase compensation
FIFOs in all channels provide lower channel-to-channel skew in bonded channel
configurations.
Non-Bonded Channel Configurations
The following functional modes support non-bonded transmitter channel
configuration:
■
■
■
■
■
■
■
PCIe ×1—Gen1 and Gen2 (Gen2 for Arria II GZ only)
Gigabit Ethernet (GIGE)
Serial RapidIO (SRIO)
SONET/SDH
SDI
Common Public Radio Interface (CPRI)/OBSAI
Basic (except Basic ×4 mode)
Figure 2–6 on page
Figure 2–5 on page
2–11), resulting in lower channel-to-channel clock skew.
2–8, resulting in higher channel-to-channel clock
Arria II Device Handbook Volume 2: Transceivers
2–7