EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 460

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–74
Arria II Device Handbook Volume 2: Transceivers
Serial Rapid I/O
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications and network processors, system memories, and
peripheral devices.
The Serial RapidIO physical layer specification defines three line rates—1.25 Gbps,
2.5 Gbps, and 3.125 Gbps. It also defines two link widths—single-lane (×1) and
bonded four-lane (×4) at each line rate. Arria II GX and GZ transceivers support only
single-lane (×1) configuration at all three line rates. You can instantiate four ×1
channels configured in Serial RapidIO mode to achieve one non-bonded ×4 Serial
RapidIO link. The four receiver channels in this ×4 Serial RapidIO link do not have
lane alignment or deskew capability.
Arria II GX and GZ transceivers, when configured in Serial RapidIO functional mode,
provide the following PCS and PMA functions:
■
■
■
■
■
Arria II GX and GZ transceivers do not have built-in support for some PCS functions,
such as pseudo-random idle sequence generation and lane alignment in ×4 mode.
Depending on your system requirements, you must implement these functions in the
logic array or external circuits.
8B/10B encoding and decoding
Word alignment
Lane synchronization state machine
Clock recovery from the encoded data
Serialization and deserialization
Chapter 1: Transceiver Architecture in Arria II Devices
December 2010 Altera Corporation
Functional Modes