EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 587

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–8. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
December 2010 Altera Corporation
Reset Signals
Output Status Signals
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_freqlocked
pll_locked
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in automatic lock mode, use the reset sequence shown in
As shown in
CDR in automatic lock mode:
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, and rx_digitalreset signals
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for the rx_freqlocked signal to go high (marker 7).
5. After the rx_freqlocked signal goes high, wait at least 4 s and then de-assert the
busy
between markers 1 and 2).
asserted during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted, after which rx_analogreset is de-asserted. After you
de-assert rx_analogreset, the receiver CDR starts locking to the receiver input
reference clock.
rx_digitalreset signal (marker 8). The transmitter and receiver are ready for data
traffic.
1
1 μs
Figure
2
4–8, perform the following reset sequence steps for the receiver
3
4
Two parallel clock cycles
5
6
7
4 μs
Arria II Device Handbook Volume 2: Transceivers
8
Figure
4–8.
4–13