EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 296

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–16
Table 9–9. FPP Timing Parameters for Arria II Devices with Decompression and Design Security not Enabled
Arria II Device Handbook Volume 1: Device Interfaces and Integration
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
Notes to
(1) Use these timing parameters when you do not enable the decompression and design security features.
(2) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(3) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(4) The values listed for t
(5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(Note
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
ST2CK
DSU
DH
CH
CL
CLK
MAX
R
CD2UM
CD2CU
CD2UMC
Symbol
respectively.
1)—Preliminary
(2)
Table
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Input rise time
Input fall time
CONF_DONE high to user mode
CONF_DONE high to CLKUSR enabled
CONF_DONE high to user mode with CLKUSR option on
9–9:
DH
Table 9–9
when you do not enable the decompression and design security features.
, t
CH
, and t
CL
are applicable only for Arria II GX devices. For Arria II GZ devices, t
lists the timing parameters for Arria II devices for an FPP configuration
Parameter
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
(5)
t
CLKUSR period)
CD2CU
4 × maximum
DCLK period
Minimum
3.2
3.2
0
500
+ (8532 ×
—
—
10
—
—
—
—
55
2
2
4
8
(4)
(4)
(4)
DH
= 1 ns, t
December 2010 Altera Corporation
Fast Passive Parallel Configuration
Maximum
CH
500
500
= 3.6 ns, and t
800
800
125
150
—
—
—
—
—
—
—
—
40
40
—
—
(3)
(3)
CL
= 3.6 ns,
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—