EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 256

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Receiver Datapath Modes
Arria II devices support the following three receiver datapath modes:
■
■
■
Non-DPA
Non-DPA mode allows you to statically select the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for any
skew between the two signals. The reference clock must be a differential signal.
Figure 8–13
registered at the rising or falling edge of the LVDS_diffioclk clock produced by the
PLL. You can select the rising/falling edge option using the ALTLVDS megafunction.
Both data realignment and deserializer blocks are clocked by the LVDS_diffioclk
clock.
For Arria II GX devices, you must perform PCB trace compensation to adjust the trace
length of each LVDS channel to improve the channel-to-channel skews when
interfacing with non-DPA receivers at data rate above 840 Mbps.
The Quartus II software Fitter Report panel reports the amount of delay you need to
add to each trace for the Arria II GX device. You can use the recommended trace delay
numbers published under the LVDS Transmitter/Receiver Package Skew
Compensation panel and manually compensate the skew on the PCB board trace to
reduce the channel-to-channel skews, thus meeting the timing budget between LVDS
channels.
“Non-DPA”
“DPA Mode”
“Soft CDR Mode”
shows the non-DPA datapath block diagram. Input serial data is
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
December 2010 Altera Corporation
Differential Receiver