EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 146

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–42
Figure 5–35. PLL Reconfiguration Scan Chain for Arria II Devices
Notes to
(1) The Arria II GX PLLs and Arria II GZ left and right PLLs support
(2) i = 6 for Arria II GX devices, i = 6 or 9 for Arria II GZ devices.
(3) This figure shows the corresponding scan register for the K counter in between the scan registers for the charge pump and loop filter. The
Arria II Device Handbook Volume 1: Device Interfaces and Integration
scanclkena
configupdate
scandataout
K counter is physically located after the VCO.
scandone
scandata
Figure
inclk
scanclk
5–35:
Reconfiguring the PLL components in real time allows you to switch between two
such output frequencies in a few microseconds. You can also use this feature to adjust
clock-to-out (t
This approach eliminates the requirement to regenerate a configuration file with the
new PLL settings.
PLL Reconfiguration Hardware Implementation
The following PLL components are reconfigurable in real time:
■
■
■
■
■
Figure 5–35
shifting their new settings into a serial shift-register chain or scan chain. Serial data is
the input to the scan chain with the SCANDATAPORT and shift registers are clocked by
SCANCLK. The maximum SCANCLK frequency is 100 MHz. Serial data is shifted through
the scan chain as long as the SCANCLKENA signal stays asserted. After the last bit of data
is clocked, asserting the configupdate signal for at least one SCANCLK clock cycle
causes the PLL configuration bits to be synchronously updated with the data in the
scan registers.
from m counter
from n counter
/Ci (2)
Pre-scale counter (N)
Feedback counter (M)
Post-scale output counters (C0 to C6 for Arria II GX devices, C0 to C9 for Arria II GZ
devices)
Post VCO divider (K)
Dynamically adjust the charge pump current (Icp) and loop filter components
(R and C) to facilitate reconfiguration of the PLL bandwidth
/Ci-1
shows how you can dynamically adjust the PLL counter settings by
CO
) delays in real time by changing the PLL output clock phase shift.
PFD
C0
to
/C2
C6
counters.
(Note 1)
LF/K/CP (3)
/C1
Chapter 5: Clock Networks and PLLs in Arria II Devices
/C0
VCO
December 2010 Altera Corporation
/m
PLLs in Arria II Devices
/n