EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 154

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–50
Table 5–21. Dynamic Phase-Shifting Control Signals for Arria II Devices (Part 2 of 2)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
SCANCLK
PHASEDONE
Signal Name
Table 5–22
PHASECOUNTERSELECT setting.
Table 5–22. Phase Counter Select Mapping for Arria II Devices
To perform one dynamic phase-shift, follow these steps:
1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required.
2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse allows one
3. Deassert PHASESTEP.
4. Wait for PHASEDONE to go high.
5. Repeat steps
Note to
(1) C7 to C9 counter are only available for Arria II GZ devices.
phase shift.
phase-shifts.
PHASECOUNTERSELECT[3]
Table
Free running clock from core used in
combination with PHASESTEP to enable,
disable, or both dynamic phase shifting. Shared
with scanclk for dynamic reconfiguration.
When asserted, this indicates to the core logic
that the phase adjustment is complete and the
PLL is ready to act on a possible second
adjustment pulse. Asserts based on internal
PLL timing. Deasserts on the rising edge of
scanclk.
lists the PLL counter selection based on the corresponding
5–22:
0
0
0
0
0
0
0
0
1
1
1
1
1
through
Description
4
as many times as required to perform multiple
[2]
0
0
0
0
1
1
1
1
0
0
0
0
[1]
0
0
1
1
0
0
1
1
0
0
1
1
Chapter 5: Clock Networks and PLLs in Arria II Devices
GCLK, RCLK, or
I/O pin
PLL
reconfiguration
circuit
[0]
0
1
0
1
0
1
0
1
0
1
0
1
(Note 1)
Source
December 2010 Altera Corporation
All Output Counters
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
C5 Counter
C6 Counter
C7 Counter
C8 Counter
C9 Counter
M Counter
PLLs in Arria II Devices
PLL
reconfiguration
circuit
Logic array or I/O
pins
Selects
Destination