EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 553

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric PLL-Transceiver PLL Cascading
December 2010 Altera Corporation
FPGA Fabric PLL-Transceiver PLL Cascading Rules
PLL cascade networks are single clock lines segmented by bidirectional tri-state
buffers located along the clock line. Segmentation of the PLL cascade network allows
two left PLLs to drive the cascade clock line simultaneously to provide two input
reference clocks to the CMU PLLs and receiver CDRs in different transceiver blocks.
When cascading two or more FPGA fabric PLLs to the CMU PLLs and receiver CDRs,
there must be no crossover in the cascaded clock paths on the PLL cascade network.
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Consider a design targeting the EP2AGX190FF35 device and requiring input
reference clocks to the following CMU PLLs and receiver CDRs from two left PLLs
in the FPGA fabric:
Case 1: PLL_4 is used to provide the input reference clock to the receiver CDRs in
channel 2 and channel 3 (shown in green). PLL_1 is used to provide the input
reference clock to the CMU0 PLL (shown in blue) in transceiver block GXBL1.
Example 12: Design Target-EP2AGX190FF35 Device
CMU0 PLL in transceiver block GXBL1
Receiver CDRs in channel 2 and channel 3 in transceiver block GXBL1
Arria II Device Handbook Volume 2: Transceivers
2–63