EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 273

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EP2AGX95EF29C4N

Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29C4N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
Figure 8–27. Corner and Center PLLs Driving DPA-Disabled Differential I/Os in the Same Bank
December 2010 Altera Corporation
Guidelines for DPA-Disabled Differential Channels
When you use DPA-disabled channels, you must adhere to the guidelines in the
following sections.
DPA-Disabled Channel Driving Distance
Each PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center PLLs in Arria II GX Devices
You can use a corner PLL to drive all transmitter channels and you can use a center
PLL to drive all DPA-disabled receiver channels in the same I/O bank. In other
words, you can drive a transmitter channel and a receiver channel in the same LAB
row by two different PLLs, as shown in
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Diff RX
Reference
Reference
CLK
Corner
Center
CLK
PLL
PLL
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Diff TX
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
8–27.
DPA -disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
Reference
Reference
Diff I /O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Corner
Center
CLK
CLK
PLL
PLL
Channels
separation
Channels
driven by
driven by
Corner
Center
needed
buffer
PLL
PLL
No
8–33

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