EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 533

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–24. Four Identical Channels in a Transceiver Block for Example 6
December 2010 Altera Corporation
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Transceiver
Transceiver
Transceiver
Transceiver
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Receiver
Receiver
Receiver
Receiver
1
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
CMU1 Block
CMU0 Block
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
This configuration uses only one FPGA global or regional clock resource for
tx_clkout[0].
CMU1
CMU0
PLL
PLL
Parallel Data
Parallel Data
Parallel Data
Parallel Data
/2
/2
/2
/2
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
Input Reference Clock
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
tx_clkout[0]
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
and Status
and Status
and Status
and Status
Channel 3
Channel 2
Channel 1
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
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