EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 221

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–18. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry for Arria II GX Devices
Notes to
(1) For possible reference input clock pins for each DLL, refer to
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
December 2010 Altera Corporation
Figure
Reference
Phase-Shift
Clock (2)
Circuitry
7–18:
DLL
DQS
6
Figure 7–18
the DQS/CQ and CQn pins in the device where memory interfaces are supported on
the top, bottom, and right sides of the Arria II GX device and all sides of the
Arria II GZ device.
CQn
to IOE
6
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
and
to IOE
CQn
Pin
Δt
Figure 7–19
DQS Logic
Blocks
to IOE
CQn
Pin
Δt
“DLL” on page
DQS/CQ
show how the DQS phase-shift circuitry is connected to
to IOE
Pin
Δt
DQS/CQ
to IOE
Pin
Δt
Arria II Device Handbook Volume 1: Device Interfaces and Integration
7–27.
to IOE
CQn
Pin
Δt
6
Phase-Shift
Reference
Clock (2)
Circuitry
DQS
DLL
IOE
IOE
IOE
IOE
6
to
to
to
to
DQS Logic
Blocks
(Note 1)
Δt
Δt
Δt
Δt
DQS/CQ
DQS/CQ
CQn
CQn
Pin
Pin
Pin
Pin
7–25