EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 417

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
Table 1–9. Detection Capabilities of the Run-Length Violation Circuit for Arria II Devices
■
Figure 1–32. 10-Bit Receiver Polarity Inversion
Receiver polarity inversion—This feature is available in all functional modes
except PCIe. It offers an optional rx_invpolarity port to dynamically enable the
receiver polarity inversion feature as a workaround to board re-spin or a major
update to the FPGA fabric design when the positive and negative signals of a
serial differential link are accidentally swapped during board layout.
1
Table 1–9
A high value on the rx_invpolarity port inverts the polarity of every bit of the
input data word to the word aligner in the receiver datapath. Because inverting
the polarity of each bit has the same effect as swapping the positive and negative
signals of the differential link, correct data is seen by the receiver. The
rx_invpolarity signal is dynamic and might cause initial disparity errors in an
8B/10B encoded link. The downstream system must be able to tolerate these
disparity errors.
Figure 1–32
wide datapath configuration.
PMA-PCS Interface Width
This generic receiver polarity inversion feature is different from the PCIe
8B/10B polarity inversion feature because it inverts the polarity of the data
bits at the input of the word aligner, whereas the PCIe 8B/10B polarity
inversion feature inverts the polarity of the data bits at the input of the
8B/10B decoder.
lists the detection capabilities of the run-length violation circuit.
10 bit
16 bit
20 bit
shows an example result with the rx_invpolarity feature in a 10-bit
8 bit
Output from Deserializer
0
1
0
1
1
1
1
1
0
0
rx_invpolarity = HIGH
Converted Data to Word Aligner
Minimum
Run Length Violation Detector Range
10
4
5
8
Arria II Device Handbook Volume 2: Transceivers
1
0
1
0
0
0
0
0
1
1
Maximum
128
160
512
640
1–31